In a manufacturing process of electronic devices such as semiconductor devices, a mask is formed on an etching target layer, and etching is performed in order to transfer a pattern of the mask to the etching target layer. In general, a resist mask is used as the mask. The resist mask is formed by a photolithography technique. Accordingly, a critical dimension of the pattern formed on the etching target layer is affected by a resolution limit of the resist mask formed by the photolithography technique.
With a recent high integration of the electronic devices, what is required is to form a pattern with a size smaller than the resolution limit of the resist mask. Therefore, as disclosed in Japanese Patent Laid-Open Publication No. 2011-82560, a technique has been suggested to reduce a width of an opening defined by the resist mask by depositing a silicon oxide film on a resist mask.
Specifically, in the technique disclosed in Japanese Patent Laid-Open No. 2011-82560, the silicon oxide film is formed on the resist mask by an atomic layer deposition (ALD) method. More specifically, an organic silicon-containing source gas and activated oxygen species are alternately supplied into a processing container that accommodates a workpiece. As the source gas, aminosilane gas is used.